Chip Verification

The Ready design verification division carries out ASIC and FPGA verification projects using contemporary (and legacy) verification methodologies. The verification team defines the methodology required to meet the customer objectives, build the environment using the most advanced tools and provide coverage-driven verification, random technics, and design customized coding tests. We also develop complex and useful scripts for the automation process, reducing cost and time to market. Our verification engineers execute complex SoC & IPs verification from scratch as well as upgrade existing environments as well as legacy language migration and maintenance.

Our Services

SoC verification development and testing
Advanced module/top-level SoC verification
Verification with advanced methodologies via the following languages: SystemVerilog, e (Specman), C, Assembly, SystemC, VHDL, Verilog
e-based/SystemVerilog random and constraint-driven verification
Advanced expertise in IP/SOC Verification – UVM based Verification Methodologies. UVM / eRM / OVM / VMM environments
Verification and test plan developments
Formal verification
Functional coverage analysis and closure
Mixed signal verification
Gate Level verification including SDF