RACHIP SOC UVM part 2

RACHIP SOC UVM Training

Based on “open source projects community” from the European Space Agency LEON processor

An Overview

Rachip is an R&D Center, SW & HW development services. Each year we train engineers in the arena of chip development, including Chip Design, Verification and Backend. As part of our intensive training, we decided to set up a self-training project. This program benefits both our working staff and productivity in the “open source projects community”. Please see also Self Project for Training Simple Verification Environment.

First we started with a verification environment, which uses a simple DUT. Simulation debugging cycles are short, and a simple DUT is perfect for novice workers and immature code. Once we completed coding and ran sanity checks, we had to verify the verification component correctness in LEON VHDL model, (which implements a 32-bit processor). We selected an internal block on-chip, namely: instruction and data caches. In the following LEON block diagram, this cache is encircled with a brown circle.

From LEON spec: “The instruction cache uses streaming during line-refill to minimize refill latency. The data cache uses write-through policy and implements a double-word write buffer. The data cache can also perform bus-snooping on the AHB bus.”

On this AHB bus, with multiple transactions taking place (about 9000 transactions for a typical test, executing read, write / single and burst types), we have connected our verification, as shown below:

The team was asked to study the cache interface, and write a generic monitor to support both the instruction and data cache interface. The interface is described below (single request followed by a burst one):

Another group in the verification team was selected to write a scoreboard from scratch, since its rules did not quite suit a standard available UVM scoreboard. The rules are:

Only one cache input channel can be serviced at a given time, Its request will go on the AHB bus.
There are no expected and actual ports, as in the standard scoreboard. Rather, on write request, the cache address and data will be first to enter the scoreboard and AHB transaction will be checked later. In a read request, it is the opposite.
Entries into the scoreboard are always from different kinds of ports.
The coreboard must be empty at simulation end.

These rules are demonstrated in the scoreboard code below:

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